Optical Fiber Communication Conference and Exposition (OFC) is the largest global conference and exhibition for optical communications. At OFC 2018 , ZTE released the latest research results on forward error correction (FEC) for the 400G international standard, which was successfully selected as a post-deadline paper (PDP). Different from regular OFC papers, PDP papers focus more on recency and cutting-edge technologies. This is the first time that a research achievement led and completed by a Chinese enterprise in the optical communication algorithm category was accepted as a PDP at OFC.
The pluggable digital coherent optical module, which uses single-carrier 400G, advanced DSP, and FEC algorithm to achieve a transmission distance of 90–120 km, is a key project of current international standard specifications, attracting major global manufacturers. Thanks to its technical accumulation, reasonable and predictive project planning ability, and superior implementation ability, ZTE stood out in the fierce competition.
Difficulties with FEC in Optical Communications
By adding certain redundant codes in valid transmission data and using the FEC decoding algorithm at the receiving end, transmission distance and system performance can be greatly improved. Especially in the 100G and 400G high-speed optical transport systems, the signal loss caused by optical channels and components is more serious. FEC has therefore become a necessary and key technology for system equipment, and its performance has also become a key factor that affects OSNR tolerance, an important indicator for the bidding of optical communication systems.
For a high-speed optical transport system that serves a pipeline in the transmission, highly reliable transmission requires that the FEC technology should meet the requirement of ultra-low bit error rates (BERs) ( less than 10-15). This presents a big challenge to FEC design and verification.
Verification at Ultra-Low BERs
If assuming 10-bit error as a reliability criterion, it is necessary to collect 1016 bits of data to reach the 10-15 BER in the test. Put simply, take the comparison between a 12-core 2G workstation and a 100G verification system (40 FPGAs, each having a throughput of 2.5G) as an example. To verify the 10-15 BER, a 12-core workstation needs to work continually for 10 years, and even a large 100G FPGA disk arrays have to work for 30 hours.
Accuracy of Digital Noise
Accuracy of the verification system noise can also affect the reliability of test results. Since it is hard to accurately control analog noise, digital noise becomes an essential means of verifying communication systems. In a high-speed optical transport system, the generation of digital noise requires ultra-high tailing accuracy and ultra-low BERs, and the implementation is quite difficult.
FEC Research and Verification for 400G
An advanced FEC solution that cascades staircase codes and Hamming codes has attracted widespread attention in the industry. Due to its clever structure design, the performance of staircase codes is superior to all FEC solutions in the G.975.1 standards. With less complex Hamming codes, the cascaded FEC solution provides good error-correction, low power consumption, and low latency, so it is quite suitable for large-capacity short-haul transmission scenarios.
Foreseeing the importance of the staircase code technology, ZTE's algorithm team conducted targeted research and mastered its core algorithm. With its experience in proprietary soft decoding algorithm, ZTE implemented core algorithm through software within three months after the 400G FEC draft using cascaded staircase and Hamming codes were released.
Hardware implementation and verification is crucial to standard drafting, and relevant research results are time-limited. In the middle of January 2018, ZTE evaluated whether it was possible to achieve ultra-high-speed (200 Gbps) hardware implementation of the entire cascaded FEC solution based on an FPGA and the feasibility of related research and tests. Due to high complexity in hardware implementation of the cascaded FEC algorithm as well as the highly time-consuming ultra-low BER research tests, the evaluation result was that it was impossible to achieve hardware implementation on a regular basis.
When confronted with the challenge, ZTE's wired algorithm team volunteered and made full effort to tackle the issue in February 2018. The team created a project plan in unit of hours and made best use of the recently developed 200G high-speed coding verification system. Through sufficient algorithms and iterations, the team worked out an FPGA block diagram on the fourth day of centralized research.
In addition to staircase and Hamming codec modules, the FPGA block diagram also includes complex functional modules such as block interleaver and convolution interleaver, as well as data source generation, noise generation, and error detection modules for tests. Through close cooperation between team members and day-and-night hard work in the entire month of February, the team finally determined the design of hardware implementation, compiled the FPGA code, and completed algorithm and hardware consistency verification.
ZTE's Achievement Selected as a PDP
After FPGA development and verification were completed, the time left for test was very limited. At this point, the 200 Gbps FPGA verification platform that was developed by ZTE and made a record of the highest speed among similar systems in the world played an important role. In order to ensure data accuracy and obtain more data support, all project team members worked around the clock to collect data and make data analysis, and finally finished the technical report on the complete research results and submitted it to the OFC technical committee for review one hour before the OIF PDP deadline.
After testing the cascaded staircase and Hamming code solution on ZTE's 200 Gbps FPGA verification platform, the team found an error flare in the solution that might be set as the 400G international standard, which caused its actual performance to be lower than what is expected in the standard. Through further research, the team located the root cause of this FEC error flare and provided the improvement idea and direction for eliminating the error flare to meet the expected performance. This achievement has played a key leading role in the final design of the FEC solution in the 400G international standard. Moreover, for the ultra-low-BER hardware test system based on digital noise, this research has first established a convergence rule that can guarantee highly-reliable ultra-low-BER tests and first applied this rule in the research on the FEC error floor and error flare under ultra-low BERs.
The paper was finally selected as an OFC PDP and received much attention in the industry, demonstrating ZTE’s leading position in cutting-edge technical innovation and product R&D of the global optical communication industry. As stated by Dr. Cai Yi during the OFC PDP presentation, “Since error correct codes were applied in the optical communication system in the late 1990s, the error code floor under ultra-low BERs has been a pending technical challenge for the academic community and the industry. The technological achievements made by ZTE this time have first helped to accomplish effective detection and research on error code performance under ultra-low-BERs . The fact that ZTE first identified the error flare problem with the cascaded staircase and Hamming code solution that might become the 400G international standard, and provided improvement direction as well, is the best case proving the advancement and practicality of this achievement. Even if the highest-speed detection system released before was adopted, the ultra-low-BER performance test and research that ZTE has completed within two weeks would take two years for completion, which could by no means satisfy the timeliness need for drafting international standards. The full set of ultra-low-BER performance research methods that ZTE has first created will also have a profound impact and significance to future technical research, development, and application in the industry.”
Ultra-high-speed FEC, 400G FEC standards, PDP at OFC, digital noise, ultra-low BERs