ZTE's Research Test on Ultra-High-Speed FEC Leads Development of the Latest 400G FEC Standards

Release Date:2018-08-16  Author:By Wang Weiming  Click:

Optical Fiber Communication Conference and Exposition (OFC) is the largest global conference and exhibition for optical communications. At OFC 2018 , ZTE released the latest research results on forward error correction (FEC) for the 400G international standard, which was successfully selected as a post-deadline paper (PDP). Different from regular OFC papers, PDP papers focus more on recency and cutting-edge technologies. This is the first time that a research achievement led and completed by a Chinese enterprise in the optical communication algorithm category was accepted as a PDP at OFC.
The pluggable digital coherent optical module, which uses single-carrier 400G, advanced DSP, and FEC algorithm to achieve a transmission distance of 90–120 km, is a key project of current international standard specifications, attracting major global manufacturers. Thanks to its technical accumulation, reasonable and predictive project planning ability, and superior implementation ability, ZTE stood out in the fierce competition. 

Difficulties with FEC in Optical Communications
By adding certain redundant codes in valid transmission data and using the FEC decoding algorithm at the receiving end, transmission distance and system performance can be greatly improved. Especially in the 100G and 400G high-speed optical transport systems, the signal loss caused by optical channels and components is more serious. FEC has therefore become a necessary and key technology for system equipment, and its performance has also become a key factor that affects OSNR tolerance, an important indicator for the bidding of optical communication systems. 
For a high-speed optical transport system that serves a pipeline in the transmission, highly reliable transmission requires that the FEC technology should meet the requirement of ultra-low bit error rates (BERs) ( less than 10-15). This presents a big challenge to FEC design and verification. 

Verification at Ultra-Low BERs
If assuming 10-bit error as a reliability criterion, it is necessary to collect 1016 bits of data to reach the 10-15 BER in the test. Put simply, take the comparison between a 12-core 2G workstation and a 100G verification system (40 FPGAs, each having a throughput of 2.5G) as an example. To verify the 10-15 BER, a 12-core workstation needs to work continually for 10 years, and even a large 100G FPGA disk arrays have to work for 30 hours. 

Accuracy of Digital Noise
Accuracy of the verification system noise can also affect the reliability of test results. Since it is hard to accurately control analog noise, digital noise becomes an essential means of verifying communication systems. In a high-speed optical transport system, the generation of digital noise requires ultra-high tailing accuracy and ultra-low BERs, and the implementation is quite difficult. 

FEC Research and Verification for 400G
An advanced FEC solution that cascades staircase codes and Hamming codes has attracted widespread attention in the industry. Due to its clever structure design, the performance of staircase codes is superior to all FEC solutions in the G.975.1 standards. With less complex Hamming codes, the cascaded FEC solution provides good error-correction, low power consumption, and low latency, so it is quite suitable for large-capacity short-haul transmission scenarios. 

Foreseeing the importance of the staircase code technology, ZTE's algorithm team conducted targeted research and mastered its core algorithm. With its experience in proprietary soft decoding algorithm, ZTE implemented core algorithm through software within three months after the 400G FEC draft using cascaded staircase and Hamming codes were release