FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

1 ETSI Standard and Power Amplifier Characteristics
    In 1992, the US Federal Communications Commission allocated a spectrum in the S-band (2.3GHz) for nationwide broadcasting of satellite-based digital audio radio. Digital radio broadcast via satellite provides a means of delivering high quality audio channels and associated services to fixed and mobile receivers [1]. New standards for satellite radio, such as the European Telecommunications Standard Institute Satellite Digital Radio (ETSI-SDR), are still being developed and deployed [2]-[4]. Authors in [5]-[7] have reported some work on FPGA implementation based on digital audio and video broadcasting standards, but not much has been done for the ETSI-SDR standards. Although ETSI-SDR standards are fairly new, they are becoming popular.

    One of the challenges of implementing an ETSI-SDR system is the nonlinear characteristics of the power amplifier (PA). A power-efficient RF amplifier should use a small amount of DC supply power; but unfortunately, there is a trade-off between efficiency and linearity [8]. PAs are most efficient when they are driven close to their saturation, which is also the most nonlinear region of operation. The quadrature amplitude modulation (QAM) or quadrature phase-shift keying (QPSK) signals from the ETSI-SDR are amplified by a nonlinear PA. This not only degrades system performance but also creates out-of-band power leakage that interferes with the systems operating in adjacent channels [9], [10]. The challenges imposed by nonlinearity in the PA are very complex. A back-off of 6-9 dB in input power is common when operating a PA and results in decreased efficiency and increased OPEX. Extending the linear region of operation of a weakly linear PA and decreasing the input power back-off reduces CAPEX and OPEX in ETSI-SDR systems.

    An amplifier is linear if its gain is constant throughout the range of the input signal. If this gain is not linear, the output signal is distorted by clipping. The DC bias point is the most important factor in determining the relationship between PA nonlinearity and efficiency. In a real amplifier, the gain A(s (t )) and phase-shift Φ (s (t )) are functions of the input signal s (t ). The complex transfer function is dependent on the amplifier input power and is given by

    As a result, the gain decreases and phase-shift changes as the level of the input signal drives the amplifier into its saturation region. The PA output amplitude and phase characteristics are known as AM-AM characteristics and AM-PM characteristics, respectively.
Fig. 1 shows typical characteristics of a PA [11]. It is possible to obtain the amplitude-modulated (AM)-AM and AM-phase-modulated (PM) characteristics as a function of complex input signal sample [12], [13]. For an nth complex input sample zn with a magnitude  zn  and a phase arg (zn), the complex transfer function of the nonlinear PA is given by

    where AM ( zn  2) and PM ( zn 2) are the polynomial functions derived from the AM-AM and AM-PM characteristics, and  zn 2 is the power of the nth complex input sample. For a nonlinear PA without memory, using AM-AM and AM-PM characteristics is sufficient to model the PA’s behavior. The complex transfer function takes the form

    where N  is the number of polynomial terms, and ak is the k th polynomial coefficient. The complex transfer function is modeled as a polynomial function of current and previous complex input signal samples. Detailed discussion of this type of PA modeling with references can be found in [13].

    Nonlinearity in a PA is measured by factors such as 1 dB compression point, third order intercept point (IP3), and adjacent channel power ratio and harmonics. One of the undesired products of PA non-linearity is inter-modulation distortion (IMD). In an ETSI-SDR system using QAM modulation, IMD manifests itself in the form of spectral regrowth. This causes in-band distortion and leakage in adjacent channels as a result of spectral spreading. Spectral regrowth degrades the quality of signal and causes adjacent channel interference.

    Techniques are required to mitigate the undesired effects of the PA in an ETSI-SDR system. There is a trade-off between efficiency and linearity when using RF PAs. At the base station, linearity in the PA is more important than efficiency [14]. A linearizer is expected to maintain a constant gain at the PA output before the PA reaches saturation. Using linearization, the input signal back-off can be decreased, and a higher level of input signal can be used to drive the PA without degrading output signals. The linearizer type chosen depends on efficiency, complexity, modulation scheme, bandwidth, adjacent channel interference, and dynamic range. Various schemes are classified according to their functionality, architecture, and application. Details of these schemes and their techniques are described in [8], [10], [14]-[16]. A common linearization technique is predistortion. This technique provides an inexpensive solution in which a nonlinear circuit is inserted between the input signal and the PA. The nonlinear circuit generates IMD products inverse to that produced by the PA and thereby cancels the effect of the PA nonlinearity. This can be viewed as the predistorter having characteristics inverse to the real PA AM-AM curve in Fig. 1. There has been a reasonable amount of research carried out in this area [17]-[21].

2 Design of a Linearizer for the ETSI Radio Interface Standard
    The linearizer design uses a look-up-table (LUT)-based predistortion algorithm. The envelope of the complex input sample is used for LUT-indexing targeting the ETSI radio interface standard. ETSI TS 102 551-2 V2.1.1 (2007-08) [4] uses OFDM for IPL-MC transmission. The mode of interest is Mode-3, with OFDM at 1 k (1024 FFT length) for 1.7 MHz channel spacing. An L-band PA, suitable for use in the transmitter of ETSI-SDR base stations, was chosen (CRF24060, Cree Wireless Devices). The PA nonlinear characteristics causing signal distortion in the OFDM transmission based on ETSI-SDR standard was studied, and nonlinear gain characteristic equations were developed. Using measured data of the PA, the polynomial functions of the AM ( zn 2) and PM ( zn 2) were obtained:

    This digital-predistortion (DPD) linearizer is designed to correct 3rd and 5th order IMD products by adaptively developing the inverse characteristics of the PA. This cancels the effects of the PA nonlinearity. The relationship between the input, V in , the PA output without DPD, V no-DPD , the DPD linearizer output, V linearizer , and the overall system output with correction, V with-DPD, is given by

    where k is the linear gain of the PA, and f (nl ) is the PA nonlinearity. As a result, the output of the overall system is, theoretically, linear.

    Fig. 2(a) shows the function of the DPD. The predistorter models the inverse characteristics of the PA as a function of the magnitude of the input χ(n). The output of the predistorter z (n) is amplified by the PA generating output s (n). This output is aligned for amplitude, phase, and delay and is used by the estimator. The estimator uses z (n) and the aligned output y (n) to develop the inverse coefficients of the PA given by acoeff  in (4). In this way, s(n) is as close as possible to χ (n). Modifications were made to the VHSIC hardware description language (VHDL)-based DPD linearizer components so that they could be used with the OFDM transmitter generated using MATLAB, SIMULINK, and digital signal processing (DSP) design tools in a Xilinx System Generator environment. Design parameters were changed to suit the requirements of the ETSI standard.

    The DPD consists of four components at the highest level: predistorter, capture buffers, measurements system, and parameter estimator, as shown in Fig. 2(b). The predistorter stores the predistortion coefficients for a given signal. These coefficients are obtained by processing a fixed number of samples at the PA input/output signals. The predistortion coefficients are in the form of polynomials of signal magnitude. To save hardware resources, these polynomials are implemented using LUTs addressed by magnitude of the complex sample. The predistorter module receives the 16-bit input I/Q data interpolated by 16 from the OFDM transmitter. The capture buffer collects signal samples from the transmission and observation (feedback) paths, and these samples are used by the estimation function to compute the predistortion coefficients. Data is captured and recaptured according to the standards set by the measurement system.

    A simulation test system was developed comprising a simulation model of the ETSI-SDR OFDM transmitter and a simulation model of the linearizer system. The simulation model of the L-band PA was experimentally obtained from the L-band PA gain and phase-shift characteristics. A commercially available state-of-the-art reference design from Xilinx [22], [23] was used as the basis for this DPD design. Simulations were performed in an integrated environment of MATLAB, SIMULINK, and Xilinx DSP development tools. Spectral regrowth was suppressed by 6-9 dB during testing of the PA in OFDM transmission after linearizer correction. The linearizer system design is suitable for a data rate of up to 92.16 MSPS with a signal bandwidth of 20 MHz. The designed ETSI-SDR OFDM transmitter requires a signal bandwidth of 1.5314 MHz with a data rate of 2.1511 MSPS. The design was implemented in an FPGA to verify its functionality.

3 Implementation, Results,and Analysis 
    A photograph and block diagram (with signal flow path) of the hardware setup are shown in Figs. 3 and 4. The testing hardware was built using commercially available components and evaluation boards. The designed ETSI-SDR OFDM transmitter and the DPD linearizer were implemented using the Virtex-4 FPGA XC4VSX35 speed grade -10, available on the Nallatech XtremeDSP Development Kit-IV evaluation board. Design synthesis, implementation, and generation of bit files suitable for loading onto the FPGAs were performed in the Project Navigator environment of Xilinx Integrated Software Environment (ISE) Foundation 10.1.3 software. The generated bit files were loaded onto the FPGAs using Nallatech Filesystem in Userspace (FUSE). The on-board clocks and resets were also set using FUSE. The main design clock was generated at 33.33 MHz using the onboard programmable oscillator. This clock is used to generate the clocks for the on-chip A/D and D/A converters at 33.33 MHz. A feedback clock signal was brought back to the Virtex-4 FPGA and used as an input to the digital clock manager (DCM). The feedback signal synchronizes the clocks to the digital-to-analog converter (DAC) and analog-to-digital converter (ADC) as well as the rest of the design logic. The DCM is also used to derive clocks that are used in the OFDM transmitter and DPD linearizer. The reset of the signals of the DCM was provided by the FPGA reset.

    The logic portion of the design consists of four main modules. The OFDM transmitter module was designed in the Xilinx System Generator for DSP 10.1.3 environment. 16-bit I/Q OFDM transmitter data were applied as input to the second module that up-samples the data to the predistortion sampling rate. The main 33.33 MHz clock is used for this second module. The linearizer system consists of the remaining two modules. One module includes the DPD and measurement system using the 100 MHz DCM output clock. This portion of the design, running at three times the data rate, allows the linearizer to simultaneously process three consecutive data samples. The final module consists of an embedded processor (Microblaze) running at the same 33.33 MHz clock as the up-sampled data. These DPD linearizer modules are meant for use with pure-VHDL approach in an ISE project environment. The 16-bit I/Q outputs of the DPD linearizer are the predistorted data that have the same sample rate as the on-chip DAC at 33.33 MHz. The DPD system also accepts the received baseband I/Q data from the PA output via the feedback path. These data were received from the output of the 14-bit ADC at 33.33 MHz. The 16-bit I/Q transmitted data from the DPD linearizer are rounded to 14 bits to match the maximum number of bits allowed by the DACs. Conversely, the 14-bit data received from the ADCs are zero-stuffed and used by the 16-bit input ports of the DPD linearizer. The digitally predistorted I/Q data output from the Virtex-4 FPGA are applied as input to the two separate DACs for transmission.

    The ETSI-SDR OFDM transmitter was designed and implemented in Virtex-4. This hardware implementation was a fixed-point equivalent of the MATLAB floating point design. The output signals come from the OFDM transmitter at 2.1511 MSPS and have been up-sampled by a factor of 16 to the predistortion sampling rate of 34.4176 MSPS. The channel bandwidth is 1.536 MHz with channel spacing of 1.712 MHz. There is a loss of precision that derives from the floating-to-fixed-point conversion in the design, and round-off noise is introduced into the system during FPGA implementation. The OFDM signal was re-generated at 33.33 MSPS instead of 34.4176 MSPS to match the system clock rate of 33.33 MHz. Therefore, channel bandwidth and spacing were altered by the same ratio of 1:0.9684 (1.487 MHz and 1.657 MHz for bandwidth and spacing, respectively). Altering these parameters to facilitate hardware implementation has negligible effects on the functional characteristics of the system. Analog signal processing, such as mixing, conversion, and attenuation, are self-explained in the block diagram.

    Fig. 5(a) is a capture of the OFDM signal spectrum on the Agilent 8564EC PSA. The power spectrum at the output of the test PA is shown in Fig. 5(b). The PA amplified the up-converted signal from the OFDM transmission at L-band frequency of 1.475 GHz. No DPD compensation was performed at this stage. The data rate of the signal was 33.33 MSPS for comparison with the output signal after DPD compensation. The total power of the input signal was maintained at around -8 dBm to -9 dBm, and care was taken not to drive the PA into saturation. Spectral regrowth at the shoulder was measured at 1.47 MHz from the carrier frequency for comparison with simulation results. Reduction in spectral regrowth at that fixed frequency from the carrier should be suffic ient to evaluate correction performed by the DPD linearizer.
Fig. 5(b) shows spectral regrowth of about -18 dB relative to the carrier. Figure 5(c) shows the output spectrum of the PA after the DPD linearizer has performed correction. The number of spectral averages, the sweep time, and other parameters required by the PSA for measurement remained unchanged to allow direct comparison. It is clearly shown that the spectral regrowth is reduced to -22.5 dB. Therefore, spectral regrowth was reduced, and the performance of the L-band test PA was improved after compensation by the DPD linearizer.

    The main logic of the design was developed and implemented in the Xilinx Virtex-4 XC4VSX35 FPGA device. All design timings were met at 276.48 MHz. Table 1 lists resource use in the design. The design only uses 35% of the available resources on the Virtex-4. This allows future signal processing exploration or the use of smaller devices to reduce the cost of implementation. The ETSI-SDR OFDM transmitter uses only 13% of the available resources, which shows that it is possible to implement radio standards based on software-defined-radio on small FPGA devices. After being interpolated to the predistortion rate, the OFDM transmitter consumes 24% of the total logic resources. A major portion of this use can be attributed to the cascaded interpolating filters that use 23% of the available DSP48 logic slices. The DPD linearizer uses 16% of the available resources. The Xilinx power analyzer reported a total dynamic power usage of 1.193 W in which the OFDM transmitter with the up-sampler consumes 204 mW, and the DPD linearizer uses 989 mW.

4 Conclusions
    An OFDM transmission system model suitable for L-band satellite radio was designed according to the ETSI-SDR standard specifications and implemented in FPGA. A linearizer system based on state-of-the-art reference design from Xilinx was also designed to improve non-linearity in the PA. A simulation model of the test system was developed in an integrated environment of MATLAB, SIMULINK, and Xilinx System Generator. A simulation equivalent of the PA was modeled as a memoryless polynomial from the experimentally obtained AM-AM and AM-PM characteristics. Baseband filtering, and RF up-conversion and down-conversion (to fit the PA requirements) were performed in analog. The PA outputs with and without DPD compensation were measured and compared. Spectral regrowth was suppressed by 9 dB at 1.5 MHz from the carrier. The OFDM transmitting system and DPD linearizer module were contained in the Xilinx Virtex-4 FPGA and met all timing constraints. It can therefore be concluded that DPD linearizer performance is compromised by the limited capabilities of the built-in ADC and DAC on the FPGA evaluation kit, the combined noise of components in the analog chain, and signal attenuation in the RF feedback path.

References
[1] K. Raghunandan, “Satellite digital radio brings new image to broadcasting,” in Proc. IEEE 2nd Int. Conf. on Recent Advances in Space Tech., Istanbul, June 2005, pp. 799-804.
[2] B. Cuesta, I. Moreno, A. Yun, and J. Rodriguez, “Analysis of the convergence between DVB-SH and ETSI-SDR,” in Proc. IEEE 1st Int. Conf. Advances in Satellite and Space Communic, Colmar, France, July 2009, pp. 13-18.
[3] http://www.en.wikipedia.org/wiki/Satellite_radio, “Satellite Radio,” accessed March 2010.
[4] Satellite Earth Stations and Systems; Satellite Digital Radio (SDR) Systems; Inner Physical layer of the Radio Interface; Part 2: Multiple Carrier Transmission, ETSI TS 102 551-2 V2.1.1 (2007-2008), August 2007.
[5] A. Sghaier, S. Areibi, and R. Dony, “IEEE802.16-2004 OFDM functions implementation on FPGAs with design exploration,” in Proc. FPL 2008 Int. Conf. on Field Programmable Logic and Applic., Heidelberg, Germany, Sept. 2008, pp. 519-522.
[6] A. Sghaier, S. Areibi, and B. Dony, “A pipelined implementation of OFDM transmission on reconfigurable platforms,” in Proc. CCECE 2008, Canadian Conf. Elect. Comput. Eng., May 2008, pp. 801-804.
[7] J. Garcia and R. Cumplido, “On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004,” presented at Int.Conf. Reconfigurable Comput. and FPGAs (RECONFIGURE’05), Puebla, Mexico, Sept. 2005.
[8] M. Hella and M. Ismail, RF CMOS Power Amplifiers: Theory, Design, Implementation. Norwell, MA: Kluwer Academic Publishers, 2002.
[9] D. M. Klymyshyn, “A power amplifier linearizer using adaptive polynomial predistortion,” M.S. thesis, Dept. Elect. Eng., Univ. of Saskatchewan, 1995.
[10] M. Ghadheri, “Adaptive linearization of efficient high power amplifiers using polynomial predistortion with global optimization,” Ph.D. thesis, Dept. Elect. Eng., University of Saskatchewan, 1995.
[11] Hsing-Hung Chen, Ching-Shyang Maa, Yeong-Cheng Wang, and Jiunn-Tsair Chen, “Joint polynomial and look-up-table power amplifier linearization scheme,” in 57th IEEE Semiannual Vehicular Tech. Conf. (VTC 2003), Jeju, Korea, April, 2003, vol. 2, pp. 1345-1349.
[12] R. Marsalek, P. Jardin, and G. Baudion, “From post-distortion to pre-distortion for power amplifier linearization,” in IEEE Commun. Lett., vol.7, no.7 pp. 308-310, Jul. 2003.
[13] R. Marsalek, P. Jardin, and G. Baudion, “Power amplifier linearization using pre-distortion with memory,” in Proc. 13th Int. Czech-Slovak Scientific Conf. RADIOELEKTRONIKA, Brno, Czech Republic, 2003, pp. 193-196.
[14] S. Cripps, RF Power Amplifiers for Wireless Communications, Boston, MA: Artech House Inc., Academic Publishers, 1999.
[15] S. Bruss, “Linearization Methods,” Class Lecture, Dep. Elect. Comput. Eng., University of California, Davis, April 2003.
[16] J. P. Moffatt and J. P MacEachern, “An adaptive QAM linearizer using postdistortion,” in Proc IEEE Global Telecom Conf., Dallas, TX, Nov 1989, pp. 406- 412.
[17] T. M. Nguyen, J. Yoh, C. H. Lee, H. T. Tran, and D. M. Johnson, “Modeling of HPA and HPA linearization through a predistorter: Global broadcasting service applications,” in IEEE Trans. Broadcasting, vol. 49, no.2, pp. 132-141, 2003.
[18] N. Safari, J. P. Tanem, and T. Roste, “Block based predistortion for amplifier linearization in burst type mobile satellite communications,” in Proc. IEEE 35th European Microw. Conf., Paris, vol. 3, 2005, pp.1783-1786.
[19] N. Ceylan, J. E. Mueller, T. Pittorino, and R. Weigel, “Mobile phone power amplifier linearity and efficiency enhancement using digital predistortion,” in Proc. IEEE 33rd European Microw. Conf., Munich, vol. 1, October 2003, pp. 269-272.
[20] A. Benchahed, A. Ghazel, M. Mabrouk, C. Rebai, and M. F. Ghannouchi, “RF digital predistorter for power amplifiers of 3G base stations,” in Proc. IEEE 13th Int. Conf. Elect., Circ., Syst., Nice, December 2006, pp. 999-1002.
[21] M. Franco, A. Guida, A. Katz and P. Herczfeld, “Reduction of in-band intermodulation distortion products in radio frequency power amplifiers with digital predistortion linearization,” in Proc. IEEE Int. Microw. Symp. Dig., pp. 918-921, June 2006.
[22] S. Summerfield, H. Parekh, and V. Barnes, “Digital predistortion reference design V2.0, EA2 Release Note”, Xilinx Inc. [Online]. Available: http://www.xilinx.com/publications/prod_mktg/pn2061.pdf
[23] S. Summerfield, H. Parekh, and V. Barnes, “Digital Predistortion Reference Design, Application Note XAPP1044 (v1.0.1),” Xilinx Inc., April, 2008.

[Abstract] Most satellite digital radio (SDR) systems use orthogonal frequency-division multiplexing (OFDM) transmission, which means that variable envelope signals are distorted by the RF power amplifier (PA). It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array (FPGA) platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

[Keywords] power amplifier linearization; digital predistortion; ETSI-SDR; OFDM; FPGA