A Histogram-Based Static-Error Correction Technique for Flash ADCs

1 Introduction
    An analog-to-digital converter (ADC) is an essential part of an RF receiver, but in many systems, an ADC limits performance.

    To relax the dynamic range requirements of an ADC, a voltage gain amplifier (VGA) and filters (for adjacent-channel blocking) are used before the ADC. Typically, linear analog filters with sharp transition bands and good VGA designs are used. Such filters are difficult to implement, especially in an integrated system and in newer CMOS technologies. The design of these blocks should be simplified, and more should be required of the ADCs. In today’s cellular applications, the main challenge is to reduce analog complexity as much as possible and shift it to the digital part of the system that relies on digital signal processing (DSP). Analog complexity is reduced by minimizing the number of (mostly) discrete elements, such as high-Q filters, and lowering the number of analog cascaded stages in down-conversion. Reduction in analog complexity allows the system to be more integrated and makes it more compatible with a system-on-chip (SOC) design.

    An important factor in ADC design is the power-accuracy trade-off. This is more critical in cellular applications, where portability significantly affects power consumption, especially that of the converter. A highly dynamic range in the converter is sometimes achievable at the cost of high power consumption. Calibration optimizes the power-accuracy trade-off, and the desired accuracy can be obtained with reduced power consumption. By reducing analog complexity and increasing digital complexity, calibration makes the converter more conducive to process-scaling and more compatible with newer CMOS technologies. However, this comes at the cost of increased digital complexity because a larger part of the ADC is digital rather than analog.

    In this paper, we focus on flash ADCs with low to moderate resolutions, that is, 3 to 8 bits. These resolutions are used extensively as the sub-ADC part of sigma-delta ADCs, in pipelined ADCs, or in applications ultrawideband where low resolution and very high-speed converters are needed. In a standard DCS-1800 for a low-IF receiver, a high-resolution, low-bandwidth converter is required. Such a converter can be realized using a sigma-delta ADC.
The accuracy of a flash ADC is mainly affected by the offsets of its comparators and references. To improve accuracy, components that are well-designed and comparatively large in terms of area and power are commonly used. This results in higher cost and, perhaps more importantly, longer design time and limited process-scaling if the ADC is embedded in a system on chip (SOC).

    In addition to the material presented in this paper, we give a more detailed analysis of the histogram-based static-error correction technique in [1], taking implementation issues into account. We study the transistor-implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process, and we evaluate the improvement in performance brought about by the calibration technique. We also suggest further improvements to the analog design so that analog complexity is further reduced in favor of digital complexity.

1.1 Calibration
    Calibration techniques for flash ADCs have been reported in [2]-[6]. In most of these techniques [2]-[4], [6], the analog part — especially the high-speed analog signal path — of the flash converter is affected by the calibration circuitry. In some of these techniques [3], [4], offset compensation (trimming) is performed inside the comparator structures. In [3], trimming is performed by adjusting the internal resistive loads of the comparator preamplifiers. However, these loads are often difficult to trim accurately because of their high gain and nonlinearity, and trimming might be inefficient. In [2] and [6], linear trimming is performed efficiently by adjusting the voltages generated by the reference ladder. In [2], an accurate digital-to-analog converter (DAC) generates a calibration signal, but the design of such a DAC still has a high degree of analog complexity. In [6], each comparator is chosen sequentially and calibrated. This affects the main ADC structure; specifically, extra calibration circuitry affects the high-speed input signal path. In [5], trimming is performed by adjusting the bulk voltages of the comparator input transistors to keep the high-speed signal path intact. However, the trimming is nonlinear because of the nonlinear relationship between the bulk and threshold voltages of the MOS transistor.

1.2 Algorithm Example
    A histogram-based calibration technique for flash ADCs is an example of an error-correction technique for front-end ADCs. The theory of histogram test methods is well-known [7]-[13], and in this paper, a histogram method is used to extract the equivalent input-referred offset of each comparator in the flash ADC. This is an estimation process. Trimming is then performed by adjusting the reference voltage levels in order to compensate for the static error sources. The estimation process is fully digital, and no changes are made to the comparator structure. Trimming is performed by adding arrays of analog switches that are connected to the reference taps of the comparators so that the high-speed signal path of the converter is not affected.

    To illustrate the calibration technique, behavioral-level simulations can be performed. Individual error sources can then be isolated, and their effects can be analyzed separately. In [1], a transistor-level ADC that uses the calibration technique is described, and practical implementation issues are discussed.

    In section 2, main sources of static error are modeled. In section 3, the calibration technique is described, and in section 4, the estimation process is described in mathematical detail. In section 5, the trimming process and related practical issues are discussed. In section 6, simulation results are given. Section 7 concludes the paper.

2 Examples of Static Errors
    In an n-bit flash ADC, 2n -1 reference levels are commonly generated by a resistor ladder. For each reference level, a comparator is used. The comparators compare the input signal with the reference levels, and combined, the comparators generate a thermometer code at their outputs. A digital decoder that filters out sparkle errors is usually used. Static errors affect the accuracy of the decision levels in the converter. Errors in the reference levels are mainly caused by resistor mismatch and comparator offsets. These two errors can be modeled (and combined) as a voltage source, Vos , at the input of each comparator, as shown in Fig. 1(a). For a low-resolution ADC, the matching of the resistors is usually much better than the nominal resolution of the flash converter, so the reference voltages from the resistor ladder can be treated as ideal values [6]. However, this is not the case for higher-resolution flash ADCs.

    In Fig. 1(a), the comparator is assumed to be ideal, and the error voltage, Vos , in practice would be described by statistical variation over many individuals. This is shown in Fig. 1(b), where Vr,i  is the ideal reference level of the ith comparator, and Vos,i  is the corresponding offset voltage source of the ideal reference. The ith interval between two adjacent reference levels is denoted Ii. In an ideal converter, the i th interval is

    where i = 1, 2,..., 2n, and the boundaries are given by Vr,0 =-VR and
Vr,   = +VR  so that the ADC range is 2VR. In practice, these intervals are changed by offset errors, as in Fig. 1(b). In the case of large offset values, Ii may disappear, and another interval may be generated. In practice, many of the reference levels are displaced from their ideal locations, and combined with the comparator offset errors, these reference levels may overlap.

3 Calibration Technique
    To calibrate the ADC, the error voltage sources, V os,i (Fig. 1), have to be estimated and compensated for. During estimation, the offset voltage or, as in many cases, just its polarity, is determined [3], [5], [6]. In trimming, the derived offset value can be compensated for by using analog circuit-level techniques.

    In the proposed technique, estimation and trimming are performed without the comparator structure being modified. This ensures that the high-speed input signal is not adversely affected. Estimation can be performed without modifying the converter structure by relying on the input signal characteristics, as is commonly done in histogram-based test methods.
The basis of the proposed technique is shown in Fig. 2. The probability density functions (PDFs) of the input and output signals of the converter are f in(x ) and f out(x ), respectively. The reference voltage of the ADC is VR, and conversion is only valid for inputs in the range -VR < V in < VR  because the ADC would otherwise saturate at either end.
An ADC system operates in normal or calibration mode. In normal mode, the input signal, V in, is connected to the flash ADC input (node x  in Fig. 2), and the ADC converts normally. In calibration mode, the output of the PDF generator is connected to the ADC input. The PDF generator produces an analog signal with a known probability density function, f in(x ). The output PDF, f out(x ), is a quantized version of f in(x ). The output PDF is a discrete function in terms of Ii. The input PDF, however, is a continuous function. Because of static errors, the two PDFs are not equal. In histogram-based calibration, the difference between these two PDFs is used to extract the ADC errors.

    Fig. 3 shows an n -bit flash ADC that uses histogram-based calibration. The calibration units are indicated by the dashed line. An array of multiplexers (MUX) is used to select a set of comparators for calibration. The outputs of the array are connected to the interval detector block. This block determines which intervals, Ii (i = 1, 2,...,16), the input samples belong to. The counter records the number of samples for each interval. The ideal number of samples for each Ii is calculated because the input PDF must be known with reasonable accuracy.

    The estimation block estimates the error voltage source, Vos,i, by using the difference between Ni and Ni , where Ni is the desired number of samples belonging to Ii , and Ni ( ~ denotes the non-ideal case) is the measured number of samples belonging to Ii. The estimations are then used by the trimming block to compensate for static errors. As described in section 5, this trimming block compensates for ADC error by adjusting the voltage taps of the resistor ladder. This adjustment changes the ADC reference levels, which are generated by the reference selection block.

4 Offset Error Estimation
    For simplicity, the proposed calibration technique is used in a flash ADC with 16 decision levels, which corresponds to a resolution of n = 4 bits. The calibration technique is then extended to higher resolutions that have greater hardware complexity. In an IC implementation, extending the resolution limits the number of blocks, (which grows exponentially with ADC resolution) so that the critical area does not increase too much.

4.1 Estimation for a Low-Resolution ADC
    If the PDF circuit generates an analog signal with a uniform distribution (constant PDF) in the range [-VR, VR ], then for an ideal 4-bit converter, and for every sufficiently large batch of N input samples, on average

    samples in each interval i = 1, 2,..., 16. In a non-ideal 4-bit converter with interval Ii, as in Fig. 1(b), the expected number of samples is

    By rearranging (3), a recursive expression is obtained:

    Equation (4) can now be used to estimate the offset values, assuming
Vos,0 = Vos,16 = 0. According to (4), comparators 1 and 15 give two initial estimated values:

    Either one of (5) or (6) is a sufficient starting condition for the calibration algorithm. However, to minimize computational error accumulation during error estimation, the offset errors related to comparator 2 to 7 are estimated using the initial condition (5), and offset errors related to comparators 8 to 14 are estimated using initial condition (6).

    For large offset values, as shown in Fig. 1(c), Ii  may disappear, creating a negative interval. In the case of an overlap, (4) must be modified so that the estimation can handle errors given by

    This modified version of (4) is used instead of (4). The case of small offset values (Vos,i) in comparator 1 is shown in Fig. 4(a), where (5) is valid. For large error values, the reference level may be pushed below the bottom voltage -VR, as in Fig. 4(b). In this case, Vos,1 is decreased during trimming until the situation shown in Fig. 4(a) is reached. Again, (5) is valid and can be used in the estimation process. The same strategy is used for the upper-end using a modified version of (6).

4.2 Extending to Higher Resolutions
    To extend the low-resolution technique to a general n -bit converter, a segmented structure can be used (Fig. 5). This structure saves hardware for higher-resolution ADCs because a substantial part of the hardware grows linearly rather than exponentially. These benefits are described in more detail in [1].

    In the segmented approach, m = 2n - 1 comparators are divided into 16 = 24 subgroups (starting with the original 4-bits). Each group consists of i = 2n - 4 comparators, except for the last group, which contains i - 1 comparators. Sixteen multiplexers are used to choose the output of one comparator from each group and connect these to the 16 -decision-level estimation block. At any time during the calibration, 16 comparators are chosen and their offsets are estimated. The results are stored in a RAM. Then, another set of 16 comparators is selected for the estimation. This procedure continues until all offsets of all comparators have been estimated and stored in the RAM. Only one state, corresponding to a standard 4-bit flash ADC, contains i - 1 comparators. This is the state when the first input of each multiplexer is chosen.

5 ADC Trimming Process
    We take the trimming approach suggested by Chen et al. in [6]. Besides having single LSB steps for the ideal reference voltages, the resistor ladder also generates smaller steps, that is, fractions of an LSB to allow the reference voltages to be more finely adjusted. This implies that trimming is done without any changes being made to the comparator.

    The approach is shown in Fig. 6. An appropriate voltage tap is selected by the trimming circuit in order to compensate for the offset value. In the resistor ladder, the coarse taps generate the ideal reference voltages, Vr,I . In addition, there are M  resistors between two consecutive coarse taps that generate M - 1 fine taps. Each fine tap generates a voltage of Vr,i +δVr ,where

is the fine-level step — a fraction of the

original coarse LSB step.

    Our aim is to create a calibration process that does not adversely affect the performance of the ADC operating in normal mode. However, in practice, this is not possible. Any calibration changes or influences the ADC structure, and this can affect the overall performance.

    Because more switches are added to the ADC’s design (Fig. 6), kickback noise, a well-known problem, emerges. In a clocked comparator, the large variations on the regeneration nodes in the latch circuit are fed back through a parasitic capacitor to the sensitive inputs of the comparator. This disturbs the input and reference voltages. A model of kickback noise is shown in Fig. 7 for an ordinary differential-pair comparator input stage.

    To simulate the effects of kickback noise, a dynamic comparator with relatively large kickback is chosen. This comparator is used in a 6-bit flash ADC architecture with a 0.5 V signal range, that is, VR = 0.25 V. The number of sub-LSB steps is M = 4, see (8). The amplitude distribution for simulated kickback in different comparators is shown in Fig. 8.
The effect of the kickback noise depends on the reference level and the impedance of the resistor ladder at a particular node. If resistance between the taps of the ladder is very low, the kickback is very small. The noise amplitude is proportional to the impedance of each tap of the resistor ladder:

    where i = 1, 2,...,2n - 1 is the tap number, and R  is the unit resistance of the reference ladder. According to (9), a symmetrical shape can be expected. However, the amount of kickback noise also depends on the input signal level as well as the reference level created by the voltage and capacitance differences between the gate and drain of input transistors. In particular, the values of the parasitic capacitors, Cgs and Cgd , change. Therefore, simulated noise is asymmetrical. In Fig. 8, we compare the normalized kickback noise levels for ideal and voltage-dependent cases.

    When extra switches are inserted for selecting finer reference levels, more decoupling capacitance is, by implication, added to different taps in the resistor ladder. Adding trimming circuitry does affect kickback noise but in a positive way.

    An increased time constant is an important problem when the resistor ladder charges the comparator input. Using analog switches that are too small in order to save area makes the problem worse. However, the time constant appears as a configuration time, T conf, which is the time the system takes to settle after the trimming command has been applied (Fig. 9). The perturbation is the effect of the kickback noise. The amplitude of the kickback noise is Vn, and the residual kickback error, caused by the resistor ladder’s long settling time in response to kickback disturbance, is ΔVn .

    The additional analog switches are the configuration switches, and their on/off state is changed at the end of each calibration cycle. During the converter’s normal operation, their state is fixed. Depending on the resistance of the resistor ladder and the size of the switches, the configuration time differs from a few clock cycles to several. The design of the circuits must include a time constant that is negligible compared with the overall calibration time. A more detailed picture of the effect of kickback noise on the calibration technique is given by the transistor-level simulation in [1]. The simulation uses a 65 nm CMOS with
1.2 V power supply.

6 Simulation Results
    To determine the efficiency of the proposed calibration technique, a behavioral-level model of an 8-bit flash ADC using the segmented calibration technique was designed and simulated. A triangular signal generator (TSG) was used to realize a uniform distribution. The effects of an unwanted, non-uniform distribution caused by, for example, nonlinearity are discussed in [1]. The TSG, was configured so that a triangular waveform with a frequency of about 100 kHz was obtained, and the sampling frequency of the ADC was a modest 400 MHz.
The system design parameters and applied-error sources are shown in Table 1. Each calibration cycle contains the estimation of equivalent offset voltages for a set of 16 comparators chosen by the multiplexer array. In the case of interval overlap, one more calibration cycle is required. Further on, two calibration cycles are required to fully compensate for the TSG comparator offsets. Because an 8-bit converter is being studied, there are 16 sets of comparators to trim, and 64 cycles are needed to fully estimate and trim all the error sources in the ADC structure.

    The estimation was implemented in register-transfer level (RTL) and synthesized on a Xilinx Spartan 3 FGPA. The post-synthesis code was used in the simulations, and 693 slices, 532 slice flip flops, and 1280 four-input lookup tables were also used.

    One hundred Monte Carlo analyses were run, and the performance of the ADC before and after calibration was measured. The static performance in terms of DNL and INL is shown in Figs. 10(a) and (b), respectively. For about 98% of the Monte Carlo runs, the converter’s performance considerably improved. After calibration, the DNL was reduced on average from 4 to 0.5 LSB, and the INL was reduced on average from 4.2 to 0.35 LSB. The failing 2% were cases where the offset was large enough to end up outside the correctable range.

7 Conclusions
    This paper describes a calibration technique for flash ADCs that is based on a histogram test method. The ADC is calibrated without its structure being adversely affected. Estimation is performed digitally, and trimming is performed by adjusting the comparator reference voltages through arrays of analog switches.

    A behavioral-level 8-bit flash ADC was designed, and typical errors were added to the comparators, resistor ladder, and PDF generator. The results of 100 Monte Carlo analysis show that converter performance was improved considerably in 98% of the runs.

    This work can be used as a grounding for the study and implementation of ADC calibration techniques. Prospects and limitations of the technique are also highlighted in this work. An IC implementation of an ADC using the proposed calibration technique is detailed in [1].

References
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Biographies

Armin Jalili (arminj@ec.iut.ac.ir) received his B.Sc. and M.Sc. degrees in electrical engineering from Isfahan University of Technology (IUT) in 2004 and 2006. He is currently working towards his Ph.D. degree in electrical engineering at IUT. His research interests include ADC design.

J. Jacob Wikner (jacob.wikner@liu.se) received his Ph.D. from the Department of Electrical Engineering, Link?ping University, Sweden, in 2001. He has worked as a research engineer at Ericsson Microelectronics, senior analog design engineer at Infineon Technologies, and senior design engineer and chip architect at Sicon Semiconductor. Dr. Wikner has been an associate professor at Link?ping University since 2009. His research interests include biologically inspired architectures, high-speed ADC and DAC, and general analog and mixed-signal design. He holds six patents, has published 40 scientific papers, and has co-authored “CMOS Data Converters for Telecommunications.” He is the co-founder of CogniCatus and AnaCatum Design.

Sayed Masoud Sayedi (m_sayedi@cc.iut.ac.ir) received his B.Sc. and M.Sc. degrees in electrical engineering from Isfahan University of Technology (IUT), Iran, in 1986 and 1988. He received his Ph.D. degree in electronics from Concordia University in 1996. From 1988 to 1992, and since 1997, he has worked at IUT, where he is currently an associate professor in the Department of Electrical and Computer Engineering. His research interests include VLSI fabrication processes, low power VLSI circuits, vision sensors, and data converters.

Rasoul Dehghani (dehghani@cc.iut.ac.ir ) received his B.S.E.E., M.Sc., and PhD degrees in electrical engineering from Sharif University of Technology (SUT), Iran, in 1988, 1991 and 2004. From 1987 to 1991, he worked on design and implementation of different electronic circuits and systems at SUT. From 1991 to 1998, he was involved in implementing various electronic circuits focused on industrial applications. From 1998 to 2004, he worked with Emad Co. in Tehran and Jaalaa Company in Kuala Lumpur as a senior design engineer. Since 2006, he has been an assistant professor at IUT. His research interests include RF IC design for wireless communication, frequency synthesis, and low-voltage low-power circuits.

[Abstract] High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high accuracy make the analog components in a converter more complex, and this complexity causes more power to be dissipated than if a traditional approach were taken. A static calibration technique for flash analog-to-digital converters (ADCs) is discussed in this paper. The calibration is based on histogram test methods, and equivalent errors in the flash ADC comparators are estimated in the digital domain without any significant changes being made to the ADC comparators. In the trimming process, reference voltages are adjusted to compensate for static errors. Behavioral-level simulations of a moderate-resolution 8-bit flash ADC show that, for typical errors, ADC performance is considerably improved by the proposed technique. As a result of calibration, the differential nonlinearities (DNLs) are reduced on average from 4 LSB to 0.5 LSB, and the integral nonlinearities (INLs) are reduced on average from 4.2 LSB to 0.35 LSB. Implementation issues for this proposed technique are discussed in our subsequent paper, “A Histogram-Based Static-Error Correction Technique for Flash ADCs: Implementation Aspects.”

[Keywords] Calibration; flash ADC; offset; trimming; uniform distribution